1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to electrically writable and erasable nonvolatile semiconductor memory devices (will be called "EEPROMs" hereinafter). More particularly, the invention relates to an erasing technique for a flash memory which is a type of EEPROM.
2. Description of the Background Art
FIG. 20 is a cross section of a memory cell in a flash memory, and FIG. 21 is a block diagram of the conventional flash memory.
With reference to the figures, the memory cell is formed of a memory transistor which has a two-layered gates including a control gate 1 and a floating gate 2.
With reference to FIG. 21, a memory array 5 has memory cells shown in FIG. 20 which are arranged in a row direction and a column direction. Each memory cell has a drain region 3 connected to a bit line 6, a control gate 1 connected to a word line 7, and a source region 4 connected to a source line 17. A gate oxide film located between floating gate 2 and a semiconductor substrate 25 generally has a thickness of about 100 .ANG.. Each word line 7 is connected to an output of a row decoder 9. Each bit line 6 is connected to a Y-gate 8. Each source line 17 is connected to a source line switch 11. Y-gate 8 is controlled by a column decoder 10 to control a connecting state of bit line 6 to a sense amplifier 13 and a write circuit 12. Each of row decoder 9 and column decoder 10 receives an output of an address buffer 15 to select one word line and one set of Y-gates. Write data and read data to and from memory array 5 are externally transmitted through an I/O buffer 16. Control circuit 14 is responsive to an externally applied control signal to control an operation of each circuit block.
Then, an operation of the conventional flash memory will be described below.
The data stored in the memory cells of memory array 5 is erased by a batch processing. In the erasing operation, a high voltage is applied to source regions 4 of all the memory cells by source line switch 11, and control gates 1 are grounded. Thereby, a high electric field is applied to an oxide film between floating gate 2 and source region 4, so that a tunnel current flows, and electron accumulated in floating gate 2 are extracted and removed to source region 4. Thereby, a threshold voltage of the memory transistor viewed from control gate 1 decreases. This state is identical with a state obtained by applying ultraviolet erasing to an electrically programmable read only memory (EPROM) of an ultraviolet erasing type. A writing operation is performed similarly to that for EPROM. Specifically, a high voltage is applied to drain region 3 and control gate 1 of the memory transistor, and source region 4 is grounded. Channel electron which generates at the vicinity of the drain is injected into floating gate 2, and thus the threshold voltage of the memory transistor viewed from control gate 1 increases.
In the reading operation, a predetermined potential is applied to the control gate of the selected memory cell, and the operation is achieved by determining whether or not the current flows through the selected memory transistor. In this operation, a higher potential applied to the bit line increases an amount of the flowing current, which enables easy detection. However, if the applied potential is higher than a predetermined potential, a high electric field is applied to the oxide film located between the floating gate and the drain, so that the electron accumulated in the floating gate escapes. Therefore, the potential applied to the drain must be restricted nearly in a range from 1 V to 2 V. A current sense amplifier is used to detect the current flowing through the memory cell while restricting the drain potential.
Here, the write voltage applied to the control gate is 12 V, and the read voltage is 5 V. The memory array is formed on a p-type semiconductor 25, as shown in FIG. 20, and circuits other than the memory array is formed on p-type semiconductor and n-type semiconductor.
FIG. 22 is a specific circuit diagram of the row decoder which selects one word line in the read/write operation. Row decoder 9 is formed of an NAND gate 24 for receiving an address signal Xi and others, n-channel MOS transistors 18 and 19 having gates for receiving address signals A1 and A1, p-channel MOS transistors 21 and 22 having sources for receiving a high voltage Vpp or a power supply voltage Vcc, and n-channel transistors 23. Transistors 21-23 form a latch circuit.
Then, an operation will be described below. When all address signals Xi-Xk applied to NAND gate 24 are "H" (logically high), NAND gate 24 is in the selected state to have an output of "L" (logically low). One of signals A1-A4 goes to "H", and the other signals are maintained at "L". In this operation, only the corresponding one of complementary signals A1-A4 is "L", and the other signals are "H". It is assumed that signal A2 becomes "H". In this case, signals A1, A3 and A4 become "L", complementary signal A2 becomes "L", and complementary signals A1, A3 and A4 becomes "H". Thereby, only a node N2 becomes "L", and nodes N1, N3, and N4 become "H", so that a word line WL2 is selected. In the writing operation, since the high voltage is applied to the sources of p-channel MOS transistors 21 and 22, only word line WL2 has a high potential, ann the other word lines have the ground potential. In the reading operation, a supply voltage of 5 V is applied to the sources of p-channel MOS transistors 21 and 22, and only word line WL2 has the potential of 5 V.
As described above, the conventional flash memory is of a chip erasing type, in which the high voltage is applied to the sources and the gates are grounded for performing the chip erasing of the write data of all the memory cells.
In the chip erasing type, however, the data in all the memory cells including valid write portions is erased, so that the writing operation is required again for the valid write portions, which causes inconvenience. Thus, it will become convenient if a specific portion(s) of the memory cells can be independently erased and written.
An EEPROM allowing erasing by a sector unit is disclosed in "4 Mb 5 V-ONLY FLASH EEPROM WITH SECTOR ERASE" (by H. Stiegler et al., 1990 Symposium on VLSI Circuits, pp. 103-104). Decoders disclosed therein are in forms of READ MODE ROW DECODER and PGM/ERASE DECODER. At the time of sector erase, a negative high voltage is applied on a selected word line by the PGM/ERASE DECODER. However, the scale of a high voltage switching circuit shown in FIG. 4 is so large that its sector erase unit is 64 word lines. The high voltage switching circuit is provided outside the memory cell array because of its large scale, so that unnecessary delay can be caused in an erasing operation.